This invention relates to fabrication of integrated circuits, and in particular, to the fabrication of dual gate structures for CMOS devices.
A variety of applications utilize CMOS (Complimentary Metal Oxide Semiconductor) integrated circuits containing a dual-gate structure. FIG. 1 illustrates a structure used in making CMOS circuits. This structure comprises a silicon substrate 100 including an n-doped region 102 and an adjacent p-doped region 104. A gate dielectric region 108 overlies regions 102 and 104, and a field dielectric 106 is disposed overlying the boundary of regions 102 and 104 to assist in their isolation. A polysilicon gate region 110 overlies the gate dielectric, and a metal silicide region 112 is formed on the polysilicon gate to enhance conductivity.
Typically, fabrication of a dual-gate structure begins by forming a field dielectric region 106 over the boundary between n-doped region 102 and a p-doped region 104. (A dielectric material is an electrically insulating material, i.e., a material having a resistivity of about 106 ohm-cm or greater.) The field dielectric 106 isolates the oppositely-doped regions of the device. The gate dielectric region 108 is then formed over regions 102 and 104. The polysilicon region 110 is typically deposited over the gate dielectric 108 and field dielectric 106. The portion of the polysilicon 110 overlying the n-doped region 102 is provided with a p-type dopant such as boron or BF2, and the portion of the polysilicon 110 overlying the p-doped region 104 is provided with an n-type dopant such as phosphorus or arsenic. The refractory metal silicide layer is typically formed by the silicide process (direct deposit of metal silicide) or the salicide process (deposit of metal followed by heating).
A difficulty in the fabrication of such structures is that n-type and p-type dopants tend to diffuse more readily in refractory metal silicides than in polysilicon. Dopants thus tend to diffuse, for example, from a region of the polysilicon 110 overlying doped silicon region 102 into the silicide layer 112, laterally in the silicide layer 112, and then back into the polysilicon 110 at a region overlying the oppositely-doped region 104. Thus, n-type dopants move into a p-doped polysilicon region and vice versa. This phenomenon, referred to as cross-doping, causes undesirable shifts in threshold voltage, an important parameter in CMOS design and operation. Moreover, the problem of cross-doping is becoming more severe as the industry moves toward smaller CMOS devices. The smaller the devices, the larger the effect of cross-dopants on properties such as threshold voltage, and the closer the devices, the less distance the dopants have to laterally travel to interfere with adjacent devices.
Problems are also created by the distribution of dopants in the implanted regions of the polysilicon 110. Advantageously, the implanted dopants in the final device are located near the underlying gate dielectric 108. Typically, however, the majority of dopants lie close to the top of the polysilicon 110, and an anneal is used to diffuse the dopants toward the gate dielectric 108. However, the anneal time and temperature required to diffuse the dopants across this distance will often undesirably allow diffusion of some of the dopants laterally within the polysilicon 110 into an oppositely-doped region of the polysilicon 110, causing cross-doping. This lateral diffusion within the polysilicon 110 is a problem regardless of whether a silicide layer is present. This mechanism of cross-doping is particularly problematic where half the distance between the active regions of adjacent devices becomes comparable to the thickness of the doped regions of the polysilicon 110. In addition, the use of thinner gate dielectric layers improves device performance, but only where a relatively large concentration of dopants, advantageously about 1020 dopants/cm3 or greater, is located adjacent to the gate dielectric (resulting in what is known in the art as low poly-depletion). If sufficient dopants are not located adjacent to the dielectric layer, the use of a thinner gate dielectric will at best only marginally improve device performance.
It is also possible for dopant distribution to cause problems when forming a refractory metal silicide by a salicide process. Growth of the silicide layer in the salicide process is detrimentally affected if too many dopants, or dopant-based precipitates, are located in the top region of the polysilicon gate structure, where the silicide is formed. In addition, because the polysilicon region is typically thicker when using a salicide process, the dopant diffusion distance to the gate dielectric is often increased, thereby allowing encroachment of the underlying channel region that often leads to shorts in the device.
A process that places dopants deep within the polysilicon layer is desired. However, such a deep implant is difficult to attain. Typically, the majority of dopants will lie close to the top surface of the polysilicon regions. It is difficult to implant dopants deeper in the polysilicon without encountering undesirable effects. For example, it is possible for dopants, particularly boron, to penetrate the polysilicon during ion implantation and move into the underlying silicon substrate, or to move along certain crystallographic orientations of polysiliconxe2x80x94a phenomenon known as channeling. (Both mechanisms are referred to herein generally as penetration.) The presence of the boron in the channel region of the silicon substrate detrimentally affects the threshold voltage. Thus, implantation is performed at energies low enough to reduce penetration. Yet, where lower implantation energies are used, the concentration profile will often not be deep enough to avoid the problems discussed above.
An improved process is described in applicant""s copending application Ser. No. 08/902,044, filed on Jul. 29, 1997 and entitled xe2x80x9cProcess for Device Fabricationxe2x80x9d. In essence, devices are prepared by forming a first, relatively thin (e.g., about 300-1000 xc3x85) amorphous silicon region over the gate dielectric region. An n-type dopant is implanted at a first portion of the first amorphous silicon region, typically over the p-type region of the substrate. The n-type dopant is advantageously implanted such that substantially all of the dopant remains in the first amorphous silicon region and does not penetrate into the underlying dielectric region or the substrate. A p-type dopant species is then implanted at a second portion of the first amorphous silicon region, typically over the n-type region of the substrate.
Once the desired dopants are implanted into the first silicon region, a second amorphous silicon (or polysilicon) region is formed over the first silicon region, in essence burying the implanted dopants. Typically, a refractory metal silicide layer is formed over the second amorphous silicon region. Devices are then formed on the structure in accordance with conventional processing techniques known to one skilled in the art.
The creation of the buried implant layer hinders cross-doping that occurs through the silicide. In order for such detrimental cross-doping to occur, the dopant must diffuse from the p-doped region of the first amorphous silicon region into and through the second amorphous silicon region into the metal silicide layer, diffuse laterally within the silicide layer to the area over the oppositely-doped amorphous silicon region, diffuse back through the second amorphous silicon region into the opposite-doped region of the first amorphous silicon region, and move through the first amorphous silicon region to an area along the underlying gate dielectric.
While this process works well, it involves two implantations, each of which requires a separate photolithography step. Each photolithography requires several different operations to complete. It would be advantageous to have a new process providing protection from cross doping which involved fewer operations.
In accordance with the invention, a process for forming a dual gate structure for CMOS devices comprises the steps of a) providing a semiconductor workpiece including n-type and p-type regions and a gate dielectric region for a dual gate structure formed over the regions, b) forming over the gate dielectric region a thin layer of semiconductor doped to one type of conductivity, c) selectively removing the doped semiconductor overlying the workpiece region of like conductivity doping and d) forming a thin layer of semiconductor doped to the opposite kind of conductivity. The doped layers are then planarized as by chemical-mechanical polishing (CMP). An additional layer of undoped semiconductor can optionally be applied to bury the doped layers, and the device can be finished by coating with metal silicide in the usual fashion. This process can be completed with only one photolithography step, simplifying device fabrication by several operations.